Semiconductor device geometries continue to dramatically decrease in size. For example, existing semiconductor devices routinely include features having dimensions less than 90 nm. A challenge that has become ever more difficult as this scaling continues has been improving the contact and sheet resistance of the vias and interconnects employed to interconnect the myriad logic devices formed in or on a substrate.
The fabrication of such a via, interconnect, or other contact can include forming an insulating layer over a substrate having complementary metal-oxide-semiconductor (CMOS) devices or other logic device formed therein. Recesses or other openings are then etched or otherwise formed in the insulating layer to expose portions of the logic devices. The openings in the insulating layer are then lined with a first barrier layer which may comprise titanium, tantalum, or alloys thereof. The partially completed device may then be pre-heated in preparation for the subsequent formation of a second barrier layer. The second barrier layer typically comprises titanium, tantalum, nitride, or alloys thereof, such as may be formed by metal-organic-chemical-vapor-deposition (MOCVD).
However, the conventional processes employed to form vias or other contacts result in contacts that exhibit excessive sheet resistance Rs and contact resistance Rc. Excessive sheet resistance Rs can prevent adequate ohmic contact between vias and interconnects, and excessive contact resistance Rc can increase power requirements and decrease performance of devices incorporating the vias and interconnects.
This problem has plagued semiconductor development for some time, to the extent that many solutions have been proposed. A typical approach has been separately improving the quality of the first and second barrier layers. However, those skilled in the art now recognize that individually improving the quality of the first and second barrier layers cannot achieve the goal of reducing both sheet resistance Rs and contact resistance Rc. Moreover, the proposed solutions typically have a severe impact on throughput, often including multi-cycle treatments or depositions that undesirably consume precious process time and render manufacturing more complex.